1. Technical Field
The present invention generally relates to semiconductor devices. More particularly, the present invention relates to the integration of stacked low temperature semiconductor devices with metal-oxide-semiconductor (MOS) devices and processes.
2. Description of the Related Art
The ever increasing demand of small, portable multifunctional electronic devices has led to the continued proliferation of smart phones, personal computing devices, personal audio devices (e.g., MP3 players), as well as biomedical and security devices. Such devices are expected to support and perform a greater number of increasingly complex and sophisticated functions while consuming less and less power. Such electronic devices rely on limited power sources (e.g., batteries and/or alternative energy harvesting systems) while providing ever-increasing processing capabilities and storage capacity.
Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). These goals have been achieved in large part by scaling down the dimensions of semiconductor ICs and thus increasing device and circuit densities. Achieving higher densities calls for smaller feature sizes, smaller separations between features and layers, and more precise feature shapes. The scaling down of IC dimensions can facilitate faster circuit performance (e.g., faster switching speeds) and can lead to higher effective yield in IC fabrication processes by packing more circuits on a semiconductor die and/or more die on a semiconductor wafer. However, continued scaling also introduces considerable challenges. For example, as the minimum feature size of MOS devices has decreased, the OFF state leakage current has increased, and is rapidly approaching ON state current levels. In addition, transistor density is limited by the amount of area that is required between devices in order to electrically isolate them from each other.
Given such constraints, one method of increasing the density of transistors per unit area has been to stack transistors, as shown in FIG. 1. A MOS field-effect transistor (MOSFET) 102 is fabricated on a local substrate 104 over an inter-layer dielectric (ILD) 106, which isolates the MOSFET 102 from underlying IC devices, such as MOSFET 108. Vertical displacement, with electrical isolation provided by ILD 106, provides for an increased transistor packing density over a given area of substrate material. However, current methods of fabricating the local substrate 104, and for forming the diffused source/drain regions 110 of stacked MOSFET 102, require high-temperature processing. For example, the local substrate 104 can be formed by depositing amorphous silicon (a-Si) which is subsequently annealed at a very high temperature to recrystallize the a-Si. Similarly, formation of the source/drain regions 110 may be accomplished for example, by way of a high temperature dopant diffusion process. Such high temperature processes can lead to failures and degradation of circuitry and devices, for example due to electromigration or dopant redistribution, among others.